Certain heterostructure materials, such as Aluminum Gallium Nitride (AlGaN) and GaN, create an electron well (i.e., a sheet of electrons) at the interface between the two dissimilar materials resulting from the piezoelectric effect and spontaneous polarization effect therebetween. The resulting sheet of electrons that forms at this interface are typically referred to as a Two-Dimensional Electron Gas (“2DEG”) channel. Equally applicable is a superlattice structure having a plurality of two-dimensional hole gas (2DHG) channels. Both types of structures can be referred to as “2D×G channel(s)” devices. FETs that operate by generating and controlling the electrons in the 2D×G channel are conventionally referred to as high electron mobility transistors (“HEMTs”).
By stacking a plurality of these two-material heterostructures, and with the addition of appropriate doping in the layers to maintain the presence of the 2D×G channels when stacking a plurality of heterostructure layers, the electron sheets are able to act in parallel, allowing for greater current flow through the superlattice device. When this type of FET is “on”, the superlattice device has a lower on-resistance, relative to a single heterostructure-layer device, because the multiple 2DEG channels allow a proportionally higher current to flow between the source and drain, resulting in an overall reduction in on-resistance. This type of structure has been well suited for providing an ultra low channel resistance high frequency switch.
In SLCFETs, multiple pairs of barrier and channel epitaxial layers are grown (e.g., AlGaN/GaN) to produce multiple conducting two dimensional electron gas (2DEG) channels. Due to difficulties in pinching these off from the top, the epitaxial is instead etched into ridges and pinched off via a gate contact from the sides. Due to limits imposed on both ridge width and sidewall slope by fabrication techniques, these FETs tend to show significantly higher pinch-off voltages and electric fields than do most standard, single channel, top pinching FETs. Specifically, for top pinching standard FETs, the gate is very close to the channel—typically on the order of 5-20 nanometers (nm), thus allowing small pinch-off voltages. However, for sidewall gates pinching-off etched ridges, distances from gate to the center of the ridge typically are below 100 nm—significantly increasing the necessary pinch-off voltage.
Though one would ideally want straight ridge sidewalls, typical limits in fabrication cause these ridges to be etched with sloped sidewalls instead of straight sidewalls. Such sidewall slopes lead to larger pinch-off voltages being required for the lower channels than for the upper channels because of their wider ridge widths. In the case of very shallow slopes, such non-uniformity in the pinch-off voltage can cause the lower channels to be too wide to pinch-off since the device will break down due to high electric fields at the edge of the sidewall gates before the high pinch-off voltage can be reached. Also, a non-uniform pinch-off voltage per channel means that channels that pinch-off early no longer contribute conduction current, thus increasing the on-state resistance from its optimal.